Hybrid Parallel Prefix Adder for High Performance Computing

The design of a n-bit binary parallel adder for a VLSI circuit is trade-off between speed of operation and hardware complexity (chip area). When speed is not the concern, Ripple Carry Adder (RCA) is the best choice, because it occupies less area and has a regular structure. The delay is directly proportional to the number of bits of the adder. Today performance is much more important than chip area; the Carry Look Ahead (CLA) adder may be the right choice in which the carry bits are predicted well in advance to speed up the computation. But when the number of bits increases, the fan-in and fan-out of the CLA increases and hence speed starts to detoriate. In order to compensate this drawback parallel prefix adders are preferred. Parallel prefix adders are slight variation of CLA in which the carry bits are generated parallely without increasing the fan-in and fan-out of the computation nodes to a larger extent. The proposed PPA structure has given better optimization in power consumption, delay and power delay product. A comparative study is made between the proposed structure and existing PPA algorithms. All the circuits were simulated using Tanner EDA in 180nm technology.