Implementation of FPGA Based Incremental PID Controller Using Conventional Method and Distributed Arithmetic Algorithm

In this paper, two efficient design schemes for implementation of the Incremental Proportional-Integral- Derivative (PID) controller using Field Programmable Gate Array (FPGA) technology are presented. Conventional implementation and also Distributed arithmetic based implementation of Incremental PID controller is done. Conventional implementation contains a large number of multipliers and adders. It's not focused on optimal use of hard ware resources and do not efficiently utilize the memory-rich characteristics of FPGAs. An FPGA chip consists of a lot of memory blocks, referred to as Look-Up Tables (LUT), which can be utilized to implement efficient designs. In the Distributed Arithmetic (DA) scheme is an efficient LUT design method, and is very promising in the FPGA implementation of PID controller. Distributed arithmetic replaces multiplication by addition and shifting. The values are precomputed and placed in LUT.