Design And ASIC Implementation Of Triple Data Encryption And Decryption Standard Algorithm

The main objective of this paper is to evaluate the performance of the algorithm TDES (Triple Data Encryption Standard), used for encryption and decryption on high speed secure data transmission. The algorithm is designed and implemented for ASIC model through a hardware description language, referred as VHDL (Very High Speed Integrated Circuit Hardware Description Language). Security issues are playing dominant role in today's high speed communication systems. Every single transmitted bit of information needs to be processed into an unrecognizable form in order to be secured. This enciphering of the data is necessary to take place in real time and for this procedure cryptography is the main mechanism to secure digital information. Triple DES is based on the DES algorithm. It is very easy to modify existing software to use Triple DES. It also has the advantage of proven reliability and a longer key length that eliminates many of the attacks that can be used to reduce the amount of time it takes to break DES. However, even this more powerful version of DES may not be strong enough to protect for very much longer. The procedure for encryption is exactly the same as DES, but it is repeated three times. Hence it is named as Triple DES. The data is encrypted with the first key, decrypted 142 Dept. of Electronics and Communication Engineering Maulana Azad National Institute of Technology, Bhopal- M.P Email: friends vijay143@yahoo.co.in, sonibhavanal@gmail.com.with the second key, and finally encrypted again with the third key. Cryptography Algorithm DES contains two processes like encryption and decryption. Encryption process and decryption process both works same algorithm but they vary in the application of key. Key is placed from 1 to 16 in encryption and 16 to 1 in decryption. These two processes can be executed efficiently with the help multiplex based design. Which is incorporated at key forcing This design is capable of reducing the hardware area to 50% when compared to the conventional approach.