Reduced Leakage Current Using Domino Techniques

As the aspect ratio of the devices shrinks down, the power supply voltage should be reduced to meet low power requirements, and the threshold voltage should also be reduced to achieve high performance. This, however, leads to exponential increase in leakage current, hence the circuit's reliability is also affected. A new domino circuit is proposed with reduced power and lower leakage for wide fan-in gates. The main goal was to make domino circuits more robust and with lower leakage and without dramatic speed degradation. The technique utilized in this paper is that, the pull-up network's mirrored current is compared with its worst case leakage current and it decreases the upper and lower boundary of the voltage swing on the dynamic node. The Dynamic node's parasitic capacitance and the keeper size for very high fan-in gates are also reduced by the proposed circuit. To implement fast and robust circuits the proposed circuit can be used as a small keeper for wide fan-in gates. The footer transistor is also used to reduce the leakage current. Simulation results of wide fan-in gates are designed using Tanner in 16-nm technology.PG Scholar, Department of PG-Electrical sciences, P.A.College of Engineering and Technology. E-mail: veejaylatha@gmail.com HOD, Department of Electronics and Communication Engineering, P.A.College of Engineering and Technology. E-mail: yuvarajmuthusamy@gmail.com